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--实验题号   : Ex1-3
--项目名称   : 全加器
--文件名     : fulladder.vhd
--作者       : 
--班号.      :  
--创建日期   : 2006-03-16
--目标芯片   : EP1C6Q240C8
--电路模式   : 模式5
--时钟选择   : 
--演示说明   : 用按键6、7、8分别输入Cn-1、Bn和An，用发光二极管D2和D1分别表示和Sn与进位Cn
--功能描述   : 本文件给出了一位全加器的结构描述，调用了一位半加器和或门元件，涉及port map等语法现象。
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library ieee;
use ieee.std_logic_1164.all;

entity or2a is
port (a, b: in std_logic;
      c: out std_logic );
end entity;

architecture one of or2a is
begin
	c <= a or b;
end architecture one;

library ieee;
use ieee.std_logic_1164.all;

entity h_adder is
port (a, b: in std_logic;
    co, so: out std_logic );
end entity;

architecture beh of h_adder is
begin
	so <= not (a xor (not b));
	co <= a and b;
end architecture beh;

library ieee;
use ieee.std_logic_1164.all;

entity fulladder is
port (ain, bin, cin: in std_logic;
    cout, sum: out std_logic );
end entity;

architecture fd1 of fulladder is
  component h_adder
    port( a, b: in std_logic;
          co, so: out std_logic);
  end component;
  component or2a
    port( a, b: in std_logic; 
          c: out std_logic);
  end component;
signal d, e, f: std_logic; 
begin
  u1: h_adder port map
    (a=>ain, b=>bin, co=>d, so=>e);    
  u2: h_adder port map
    (a=>e, b=>cin, co=>f, so=>sum);
  u3: or2a    port map
    (a=>d, b=>f, c=>cout);
end architecture fd1;